1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a spacer structure design of a chip package and a fabrication method thereof.
2. Description of the Related Art
Wafer level chip scale packaging technology has been developed for chip packages. In a wafer level chip scale package, a semiconductor wafer is bonded to a glass substrate and a spacer is disposed between the semiconductor wafer and the glass substrate. After the wafer level chip scale package is formed, a dicing process is performed between each chip to form a chip package.
In the conventional chip packages, a side surface consisting of the semiconductor wafer, the spacer and the glass substrate is continuous. Because the materials of the semiconductor wafer, the spacer and the glass substrate are different, thermal expansion coefficients thereof are also different. When the conventional chip packages are exposed to a high temperature, delamination occurs between the semiconductor wafer, the spacer and the glass substrate. Therefore, water vapor and air easily permeate into the conventional chip packages to produce electrical failure therein.
Therefore, a chip package which can overcome the above mentioned problems is desired to prevent chip packages from delamination.